The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2025

Filed:

Jun. 02, 2024
Applicant:

Monolithic 3d Inc., Klamath Falls, OR (US);

Inventors:

Zvi Or-Bach, Haifa, IL;

Jin-Woo Han, San Jose, CA (US);

Brian Cronquist, Klamath Falls, OR (US);

Assignee:

Monolithic 3D Inc., Klamath Falls, OR (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10B 10/00 (2023.01); G11C 16/04 (2006.01); H10B 12/00 (2023.01); H10B 41/10 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 10/125 (2023.02); G11C 16/0483 (2013.01); H10B 10/18 (2023.02); H10B 12/50 (2023.02); H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02);
Abstract

A semiconductor device including: a first level including at least four independently controlled first memory arrays, where the first level includes first transistors; a second level disposed on top of the first level, where the second level includes second memory arrays; and a third level disposed on top of the second level, where the third level includes third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, where the second filled holes are aligned to the first filled holes with a more than 1 nm but less than 40 nm alignment error, and where the third level includes at least one SRAM memory array.


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