The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2025

Filed:

Apr. 15, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Kuo-Cheng Chiang, Zhubei, TW;

Shi-Ning Ju, Hsinchu, TW;

Ching-Wei Tsai, Hsinchu, TW;

Kuan-Lun Cheng, Hsin-chu, TW;

Chih-Hao Wang, Baoshan Township, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/785 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 27/0924 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01);
Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a plurality of nanowire structures over a channel region of a semiconductor fin structure, a source/drain feature on a source/drain region of the semiconductor fin structure, and a dielectric fin structure spaced apart from the source/drain feature and the semiconductor fin structure. A top surface of the dielectric fin structure is higher than a top surface of a bottommost one of the nanowire structures, and a bottom surface of the dielectric fin structure is lower than a bottom surface of the source/drain feature.


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