The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2025

Filed:

Jan. 12, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventor:

Jingwen Lu, Hefei, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H01L 21/76837 (2013.01); H01L 23/5283 (2013.01); H01L 23/53266 (2013.01); H01L 23/53295 (2013.01); H10B 12/0335 (2023.02); H10B 12/31 (2023.02); H10B 12/482 (2023.02);
Abstract

The present disclosure provides a semiconductor memory device and a manufacturing method thereof. The manufacturing method includes: providing a substrate having a plurality of active areas; forming a plurality of bit line structures on the substrate, where the plurality of bit line structures are sequentially provided at intervals along a first direction; forming a dielectric layer on the substrate; etching the dielectric layer, to form a plurality of contact holes and a plurality of isolation structures, where each contact hole is between the adjacent bit line structures, the plurality of contact holes and the plurality of isolation structures are alternately provided along a second direction, the first direction is not parallel to the second direction; and forming an isolation layer on a side wall of each bit line structure and a side wall of each isolation structure.


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