High speed memory device with data masking

Abstract

Aspects of the disclosure provide a semiconductor device. For example, the semiconductor device can include a first deserializer, a second deserializer, and a write data converter coupled to the first deserializer and the second deserializer. The first deserializer can be configured to convert serial data to parallel data based on a set of write clock signals, thus the parallel data has a first timing alignment with regard to the set of write clock signals. The second deserializer can be configured to generate a mask pattern based on the set of write clock signals, thus the mask pattern has a second timing alignment with regard to the set of write clock signals. The write data converter can be configured to generate valid data based on the parallel data and the mask pattern.