The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2025

Filed:

Dec. 14, 2022
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Weijun Wan, Wuhan, CN;

Yue Sheng, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5628 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/3459 (2013.01);
Abstract

A peripheral circuit of a memory device includes page buffers. Each page buffer includes a main latch, a bias latch, (N−1) data latches, and a cache latch coupled to a data path. The peripheral circuit is further configured to: in the process of programming a first physical page, disable a bit line bias function to release the bias latch to replace one of N page latches to perform a programming verification of memory states; release one of the N page latches to cache program data of one of the N logical pages of a second physical page; and in the process of programming the first physical page, store the program data of the one of the N logical pages of the second physical page in a released page latch.


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