The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 11, 2025
Filed:
Apr. 15, 2021
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Swadesh Choudhary, Mountain View, CA (US);
Mahesh Wagh, Portland, OR (US);
Debendra Das Sharma, Saratoga, CA (US);
Assignee:
INTEL CORPORATION, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/38 (2006.01); G06F 11/10 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 13/382 (2013.01); G06F 11/1048 (2013.01); G06F 13/4018 (2013.01); G06F 13/4059 (2013.01); G06F 13/4068 (2013.01);
Abstract
In one embodiment, an apparatus includes: a first link layer circuit to perform link layer functionality for a first communication protocol; and a logical physical (logPHY) circuit coupled to the first link layer circuit via a logical PHY interface (LPIF) link, the logPHY circuit to communicate with the first link layer circuit in a flit mode in which the first information is communicated in a fixed width size and to communicate with another link layer circuit in a non-flit mode. Other embodiments are described and claimed.