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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12222880 B1

PDFFull Text
Date of Patent:
Feb. 11, 2025

Filed:

Jun. 29, 2023

Stacked semiconductor device assembly in computer system

Applicant:

Rambus Inc., San Jose, CA (US);

Inventor:

Scott C. Best, Palo Alto, CA (US);

Assignee:

RAMBUS INC., San Jose, CA (US);

Attorney:

Morgan, Lewis & Bockius LLP

Primary Examiner:

Henry Tsai

Assistant Examiner:

Christopher A Daley

Int. Cl.
CPC ...
G06F 13/36 (2006.01); G06F 13/362 (2006.01); G06F 13/40 (2006.01); G11C 11/408 (2006.01); G11C 11/409 (2006.01); G11C 11/4096 (2006.01); G11C 14/00 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/50 (2006.01); H01L 23/60 (2006.01); H01L 25/065 (2023.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
G06F 13/362 (2013.01); G06F 13/4068 (2013.01); G11C 11/408 (2013.01); G11C 11/409 (2013.01); G11C 11/4096 (2013.01); G11C 14/0018 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); H01L 23/481 (2013.01); H01L 23/50 (2013.01); H01L 23/60 (2013.01); H01L 24/09 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 27/0248 (2013.01); H01L 23/48 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05552 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2225/06503 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06562 (2013.01); H01L 2924/00 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/15311 (2013.01);
Abstract

This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.

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