The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2025

Filed:

Apr. 29, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Shuai Guo, Hefei, CN;

Mingguang Zuo, Hefei, CN;

Shijie Bai, Hefei, CN;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66742 (2013.01); H01L 21/823412 (2013.01); H01L 21/823481 (2013.01); H01L 29/78696 (2013.01);
Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: depositing a thin-film stacked structure on a substrate; forming a first hole in the thin-film stacked structure; growing an epitaxial silicon pillar in the first hole; etching the thin-film stacked structure and the epitaxial silicon pillar along a first direction to form a first trench, the first trench passing through a center of the epitaxial silicon pillar and dividing the epitaxial silicon pillar into a first half pillar and a second half pillar; forming a first isolation layer; forming a first channel region of a first doping type, and forming a second channel region of a second doping type; and forming a gate dielectric layer and a gate conductive layer on a surface of each of the first channel region and the second channel region.


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