The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2025

Filed:

Aug. 09, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Wei-Yu Chen, New Taipei, TW;

An-Jhih Su, Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/03 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/49811 (2013.01); H01L 23/49816 (2013.01); H01L 23/5389 (2013.01); H01L 24/12 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/97 (2013.01); H01L 25/03 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01); H01L 21/561 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/19 (2013.01); H01L 2224/24145 (2013.01); H01L 2224/24227 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/83005 (2013.01); H01L 2224/97 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/06582 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/18162 (2013.01); H01L 2924/3511 (2013.01);
Abstract

A method for forming a chip package structure is provided. The method includes forming a first molding layer surrounding a first chip structure. The method includes disposing a second chip structure over the first chip structure and the first molding layer. The method includes forming a second molding layer surrounding the second chip structure and over the first chip structure and the first molding layer. The method includes forming a third molding layer surrounding the first molding layer and the second molding layer. The method includes disposing a third chip structure over the second chip structure, the second molding layer and the third molding layer. The method includes forming a fourth molding layer surrounding the third chip structure and over the second chip structure, the second molding layer, and the third molding layer.


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