The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2025
Filed:
Apr. 18, 2022
Applicant:
Infineon Technologies Ag, Neubiberg, DE;
Inventors:
Assignee:
Infineon Technologies AG, Neubiberg, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 21/78 (2006.01); H01L 23/055 (2006.01); H01L 23/48 (2006.01); H01L 23/538 (2006.01); H01L 21/56 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 24/82 (2013.01); H01L 21/4853 (2013.01); H01L 21/486 (2013.01); H01L 21/78 (2013.01); H01L 23/055 (2013.01); H01L 23/481 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/25 (2013.01); H01L 24/83 (2013.01); H01L 24/97 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/49816 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/2518 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/82039 (2013.01); H01L 2224/8285 (2013.01); H01L 2224/83005 (2013.01); H01L 2224/83132 (2013.01); H01L 2224/83191 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/92144 (2013.01); H01L 2224/97 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01);
Abstract
An electronic module is disclosed. In one example, the electronic module includes a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer. The first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.