The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2025

Filed:

Jun. 09, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Harry-Hak-Lay Chuang, Zhubei, TW;

Tien-Wei Chiang, Taipei, TW;

Kuo-An Liu, Hsinchu, TW;

Chia-Hsiang Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/495 (2006.01); H01L 23/552 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 23/49555 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/80 (2023.02); H01L 2224/48091 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/49176 (2013.01); H01L 2924/1443 (2013.01); H01L 2924/3025 (2013.01);
Abstract

In some embodiments, the present application provides an integrated chip. The integrated chip includes a chip comprising a semiconductor device. A shielding structure abuts the chip. The shielding structure comprises a first horizontal region adjacent to a first horizontal surface of the chip. The first horizontal region comprises a first multilayer structure comprising a first dielectric layer and two or more metal layers. The first dielectric layer is disposed between the two or more metal layers.


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