The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2025
Filed:
Mar. 10, 2023
Micron Technology, Inc., Boise, ID (US);
Paing Z. Htet, Union City, CA (US);
Akira Goda, Tokyo, JP;
Eric N. Lee, San Jose, CA (US);
Jeffrey S. McNeil, Nampa, ID (US);
Junwyn A. Lacsao, Folsom, CA (US);
Kishore Kumar Muchherla, San Jose, CA (US);
Sead Zildzic, Folsom, CA (US);
Violante Moschiano, Avezzano, IT;
Micron Technology, Inc., Boise, ID (US);
Abstract
A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.