The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2025

Filed:

May. 19, 2023
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sreenivas Subramoney, Bangalore, IN;

Stanislav Shwartsman, Haifa, IN;

Anant Nori, Bangalore, IN;

Shankar Balachandran, Bangalore, IN;

Elad Shtiegmann, Kefar Sava, IL;

Vineeth Mekkat, San Jose, CA (US);

Manjunath Shevgoor, San Jose, CA (US);

Sourabh Alurkar, Santa Clara, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0862 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0862 (2013.01); G06F 2212/602 (2013.01);
Abstract

System and method for prefetching pointer-referenced data. A method embodiment includes: tracking a plurality of load instructions which includes a first load instruction to access a first data that identifies a first memory location; detecting a second load instruction which accesses a second memory location for a second data, the second memory location matching the first memory location identified by the first data; responsive to the detecting, updating a list of pointer load instructions to include information identifying the first load instruction as a pointer load instruction; prefetching a third data for a third load instruction prior to executing the third load instruction; identifying the third load instruction as a pointer load instruction based on information from the list of pointer load instructions and responsively prefetching a fourth data from a fourth memory location, wherein the fourth memory location is identified by the third data.


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