The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2025

Filed:

May. 18, 2023
Applicants:

Beijing Boe Optoelectronics Technology Co., Ltd., Beijing, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Haisheng Wang, Beijing, CN;

Xue Dong, Beijing, CN;

Hailin Xue, Beijing, CN;

Xi Chen, Beijing, CN;

Yingming Liu, Beijing, CN;

Xiaoliang Ding, Beijing, CN;

Weijie Zhao, Beijing, CN;

Shengji Yang, Beijing, CN;

Hongjuan Liu, Beijing, CN;

Changfeng Li, Beijing, CN;

Wei Liu, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/044 (2006.01); G06F 3/041 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); G06F 3/0412 (2013.01); G06F 3/0443 (2019.05); G06F 2203/04103 (2013.01);
Abstract

An array substrate is provided. The array substrate includes a base substrate and a plurality of gate lines, a plurality of data lines, a common electrode layer and a plurality of pixel units arranged in an array disposed on the base substrate. Each of the pixel units includes a plurality of sub-pixel units defined by gate lines and data lines disposed to intersect each other laterally and vertically. The common electrode layer includes a plurality of common electrode blocks that double as self-capacitance electrodes, each of the common electrode blocks is connected with at least one wire, and the wires are in the middle of sub-pixel units of a same column.


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