The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2025

Filed:

Dec. 05, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hsiang-Ku Shen, Hsinchu, TW;

Chih Wei Lu, Hsinchu, TW;

Hui-Chi Chen, Hsinchu, TW;

Jeng-Ya David Yeh, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/76831 (2013.01); H01L 21/76897 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823475 (2013.01); H01L 21/823821 (2013.01); H01L 29/0847 (2013.01); H01L 29/66636 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 21/823468 (2013.01); H01L 29/4958 (2013.01); H01L 29/4966 (2013.01); H01L 29/4975 (2013.01); H01L 29/517 (2013.01);
Abstract

In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first sidewall spacers is different from a second depth of the first space above the first gate electrode layer.


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