The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 2025
Filed:
Jul. 18, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Ni-Wan Fan, Miao-Li County, TW;
Ting-Wei Chiang, New Taipei, TW;
Cheng-I Huang, Hsinchu, TW;
Jung-Chan Yang, Longtan Township, TW;
Hsiang-Jen Tseng, Hsinchu, TW;
Lipen Yuan, Jhubei, TW;
Chi-Yu Lu, New Taipei, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.