The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 2025
Filed:
Feb. 01, 2022
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Inventors:
Yung-Chih Tsai, Jhudong Township, TW;
Wei-Che Hsu, Tainan, TW;
Yu-Chung Yang, Hsinchu, TW;
Alexander Kalnitsky, San Francisco, CA (US);
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01);
U.S. Cl.
CPC ...
H01L 21/7682 (2013.01); H01L 21/76805 (2013.01); H01L 21/76895 (2013.01); H01L 23/5222 (2013.01); H01L 23/5283 (2013.01); H01L 23/5329 (2013.01); H01L 23/53295 (2013.01); H01L 23/535 (2013.01);
Abstract
A semiconductor structure includes a substrate and a dielectric material disposed over the substrate. A void is disposed within the dielectric material. A dielectric liner is disposed along inner sidewalls of the dielectric material proximate to the void. An inner surface of the dielectric liner defines an outer extent of the void, and the dielectric liner includes an inner liner layer and an outer liner layer.