The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2025

Filed:

Mar. 31, 2023
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Niraj Nandan, Plano, TX (US);

Mihir Mody, Bangalore, IN;

Rajasekhar Allu, Plano, TX (US);

Manoj Koul, Allen, TX (US);

Pandy Kalimuthu, Plano, TX (US);

David Stoller, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04N 23/81 (2023.01); H04N 23/84 (2023.01); H04N 23/88 (2023.01);
U.S. Cl.
CPC ...
H04N 23/81 (2023.01); H04N 23/843 (2023.01); H04N 23/88 (2023.01);
Abstract

In described examples, an integrated circuit includes first, second, third, and fourth image processing blocks, a data selection circuitry, and a pipeline memory. An input of the first image processing block receives raw image data. An input of the second image processing block is coupled to an output of the first image processing block. An input of the third image processing block is coupled to an output of the second image processing block. A first input of the data selection circuitry is coupled to an output of the first image processing block, and a second input of the data selection circuitry is coupled to an output of the second image processing block. A data input of the pipeline memory is coupled to an output of the data selection circuitry, and an output of the pipeline memory is coupled to an input of the fourth image processing block.


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