The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2025

Filed:

Dec. 01, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chung-Peng Hsieh, Hsinchu, TW;

Chih-Chiang Chang, Hsinchu, TW;

Yung-Chow Peng, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/14 (2014.01); H03K 5/131 (2014.01); H03K 5/134 (2014.01); H03K 5/24 (2006.01);
U.S. Cl.
CPC ...
H03K 5/14 (2013.01); H03K 5/131 (2013.01); H03K 5/134 (2014.07); H03K 5/2481 (2013.01);
Abstract

A delay-locked loop (DLL) circuit includes a low pass filter coupled to a phase detector, and a digitally controlled delay line (DCDL) coupled to the low pass filter. The DCDL includes an input terminal, an output terminal coupled to an input terminal of the phase detector, and stages that propagate a signal along a first path from the input terminal to a selectable return stage and along a second path from the return stage to the output terminal. Each stage includes first and second inverters that selectively propagate the signal along the first and second paths, a third inverter that selectively propagates the signal from the first path to the second path, and either fourth and fifth inverters that selectively propagate the signal along the first and second paths, or a sixth inverter that selectively propagates the signal from the first path to the second path.


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