The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 21, 2025
Filed:
Jun. 15, 2022
Silicon Storage Technology, Inc., San Jose, CA (US);
Hieu Van Tran, San Jose, CA (US);
Thuan Vu, San Jose, CA (US);
Stephen Trinh, San Jose, CA (US);
Stanley Hong, San Jose, CA (US);
Anh Ly, San Jose, CA (US);
Steven Lemke, Boulder Creek, CA (US);
Nha Nguyen, San Jose, CA (US);
Vipin Tiwari, Dublin, CA (US);
Nhan Do, Saratoga, CA (US);
SILICON STORAGE TECHNOLOGY, INC., San Jose, CA (US);
Abstract
In one example, a method of testing a plurality of non-volatile memory cells in an array of non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, comprises asserting, by the row decoder, all word lines in the array; asserting, by the column decoder, all bit lines in the array; performing a deep programming operation on the array of non-volatile memory cells; and measuring a total current received from the bit lines.