Architecture for dram control optimization using simultaneous bidirectional memory interfaces

Abstract

A computing device performs both read/write operations concurrently to a memory. Queues for read or write operations are maintained on the memory, allowing the computing device to issue concurrent read/write commands, without complex ordering/buffering circuitry. For a read operation, the memory receives the read command and buffers it in a priority order assigned thereto. The memory can perform the read command and respond with the requested response on a data bus disposed to communicate read data. For a write operation, the memory receives the write command and buffers it for processing in a priority order for that command, such as for relatively immediate processing. The memory can perform the write command using write data on a separate data bus disposed to communication write data.