The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2025

Filed:

Sep. 07, 2023
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Francesc Guim Bernat, Barcelona, ES;

Daniel Rivas Barragan, Cologne, DE;

Kshitij A. Doshi, Tempe, AZ (US);

Mark A. Schmisseur, Phoenix, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); C07F 15/00 (2006.01); G06F 12/0817 (2016.01); G06F 12/0831 (2016.01); G06F 12/1018 (2016.01); G06F 13/16 (2006.01); H04L 12/46 (2006.01); H04L 49/90 (2022.01);
U.S. Cl.
CPC ...
G06F 13/1663 (2013.01); C07F 15/0033 (2013.01); G06F 12/082 (2013.01); G06F 12/0822 (2013.01); G06F 12/0831 (2013.01); G06F 12/1018 (2013.01); H04L 12/4625 (2013.01); H04L 49/9068 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/621 (2013.01);
Abstract

In an example, there is disclosed a host-fabric interface (HFI), including: an interconnect interface to communicatively couple the HFI to an interconnect; a network interface to communicatively couple the HFI to a network; network interface logic to provide communication between the interconnect and the network; a coprocessor configured to provide an offloaded function for the network; a memory; and a caching agent configured to: designate a region of the memory as a shared memory between the HFI and a core communicatively coupled to the HFI via the interconnect; receive a memory operation directed to the shared memory; and issue a memory instruction to the memory according to the memory operation.


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