The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2025

Filed:

May. 01, 2024
Applicant:

Eliyan Corporation, Santa Clara, CA (US);

Inventors:

Curtis McAllister, Los Altos, CA (US);

Syrus Ziai, Los Altos, CA (US);

Assignee:

Eliyan Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 13/16 (2013.01); G06F 2213/16 (2013.01);
Abstract

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a memory chiplet is disclosed. The memory chiplet includes at least one memory die of a first memory type. Memory control circuitry is coupled to the at least one memory die. An interface circuit is for coupling to a host IC chiplet. The interface circuit includes data input/output (I/O) circuitry for coupling to multiple data lanes. Link directional control circuitry selects, for a first memory transaction, a first subset of the multiple data lanes to transfer data between the memory chiplet and the host IC chiplet.


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