The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2025

Filed:

Aug. 02, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Wei Ting Hsieh, Hsinchu, TW;

Kuen-Yi Chen, Hsinchu, TW;

Yi-Hsuan Chen, Taoyuan, TW;

Yu-Wei Ting, Taipei, TW;

Yi Ching Ong, Hsinchu, TW;

Kuo-Ching Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/94 (2006.01); H10B 53/30 (2023.01);
U.S. Cl.
CPC ...
H10B 53/30 (2023.02); H01L 29/516 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09); H01L 29/94 (2013.01);
Abstract

A method according to the present disclosure includes forming a bottom electrode layer over a substrate, forming an insulator layer over the bottom electrode layer, depositing a semiconductor layer over the bottom electrode layer, depositing a ferroelectric layer over the semiconductor layer, forming a top electrode layer over the ferroelectric layer, and patterning the bottom electrode layer, the insulator layer, the semiconductor layer, the ferroelectric layer, and the top electrode layer to form a memory stack. The semiconductor layer includes a plurality of portions with different thicknesses.


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