The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2025

Filed:

Sep. 21, 2022
Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventors:

Hieu Van Tran, San Jose, CA (US);

Steven Lemke, Boulder Creek, CA (US);

Vipin Tiwari, Dublin, CA (US);

Nhan Do, Saratoga, CA (US);

Mark Reiten, Alamo, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/42 (2023.01); G06N 3/08 (2023.01); G11C 16/04 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H10B 41/42 (2023.02); G06N 3/08 (2013.01); G11C 16/0425 (2013.01); H01L 29/7883 (2013.01);
Abstract

Numerous examples of an input function circuit block and an output neuron circuit block coupled to a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one example, an artificial neural network comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells organized into rows and columns; an input function circuit block to receive digital input signals, convert the digital input signals into analog signals, and apply the analog signals to control gate terminals of non-volatile memory cells in one or more rows of the array during a programming operation; and an output neuron circuit block to receive analog currents from the columns of the array during a read operation and generate an output signal.


Find Patent Forward Citations

Loading…