The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2025

Filed:

Mar. 13, 2024
Applicant:

Rambus Inc., San Jose, CA (US);

Inventors:

Frederick A. Ware, Los Altos Hill, CA (US);

Suresh Rajan, San Jose, CA (US);

Assignee:

Rambus Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G06F 1/18 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 15/78 (2006.01); G11C 5/04 (2006.01); G11C 7/10 (2006.01); G11C 11/408 (2006.01); G11C 11/4093 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H05K 1/11 (2013.01); G06F 1/184 (2013.01); G06F 13/1694 (2013.01); G06F 13/4068 (2013.01); G06F 15/7803 (2013.01); G11C 5/04 (2013.01); G11C 5/06 (2013.01); G11C 7/10 (2013.01); G11C 11/4082 (2013.01); G11C 11/4093 (2013.01); H05K 1/181 (2013.01); H05K 2201/10159 (2013.01); H05K 2201/10189 (2013.01);
Abstract

The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.


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