The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 14, 2025
Filed:
Jun. 02, 2022
National Technology & Engineering Solutions of Sandia, Llc, Albuquerque, NM (US);
Tzu-Ming Lu, Albuquerque, NM (US);
Xujiao Gao, Albuquerque, NM (US);
Evan Michael Anderson, Albuquerque, NM (US);
Juan Pedro Mendez Granado, Albuquerque, NM (US);
DeAnna Marie Campbell, Albuquerque, NM (US);
Scott William Schmucker, Albuquerque, NM (US);
Shashank Misra, Albuquerque, NM (US);
National Technology & Engineering Solutions of Sandia, LLC, Albuquerque, NM (US);
Abstract
A vertical tunneling field-effect transistor and a method for its manufacture are provided. According to methods herein disclosed, oppositely doped source and drain regions are formed, and an APAM delta layer is formed in the surface of the transistor substrate, beneath a metal gate, in electrical contact with, e.g., the source region. A dielectric layer intervenes between the substrate surface and the metal gate. An epitaxial cap layer directly over the APAM layer forms a dielectric layer interface with a dielectric layer, which is located between the epitaxial cap layer and the metal gate. A vertical channel is defined for tunneling between the APAM delta layer and an induced conduction channel adjacent to the dielectric layer interface that is formed in operation, and that is in electrical contact with, e.g., the drain region.