The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2025

Filed:

Dec. 15, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co. Ltd., Hsin-Chu, TW;

Inventors:

Wei Ju Lee, Hsinchu, TW;

Chun-Fu Cheng, Hsinchu County, TW;

Chung-Wei Wu, Hsinchu County, TW;

Zhiqiang Wu, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/02236 (2013.01); H01L 21/02532 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 27/0886 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/42392 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66636 (2013.01); H01L 29/7851 (2013.01); H01L 29/78696 (2013.01); H01L 29/0653 (2013.01); H01L 29/6656 (2013.01);
Abstract

The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a stack of first semiconductor layers and second semiconductor layers over a substrate, etching the stack to form a source/drain (S/D) recess in exposing the substrate, and forming an S/D formation assistance region in the S/D recess. The S/D formation assistance region is partially embedded in the substrate and includes a semiconductor seed layer embedded in an isolation layer. The isolation layer electrically isolates the semiconductor seed layer from the substrate. The method also includes epitaxially growing an S/D feature in the S/D recess from the semiconductor seed layer. The S/D feature is in physical contact with the second semiconductor layers.


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