The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2025

Filed:

Jun. 23, 2023
Applicant:

Rambus Inc., San Jose, CA (US);

Inventors:

Richard E. Perego, Thornton, CO (US);

Frederick A. Ware, Los Altos Hills, CA (US);

Assignee:

Rambus Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1072 (2013.01); G06F 13/1678 (2013.01); G06F 13/1684 (2013.01); G06F 13/1694 (2013.01); G11C 5/06 (2013.01); G11C 7/1045 (2013.01); G11C 7/1075 (2013.01);
Abstract

A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.


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