The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2025

Filed:

Mar. 16, 2022
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventor:

Masaru Yano, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/16 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01); G11C 29/24 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/16 (2013.01); G11C 16/0483 (2013.01); G11C 16/3445 (2013.01); G11C 16/345 (2013.01); G11C 16/3459 (2013.01); G11C 16/3468 (2013.01); G11C 29/24 (2013.01); G11C 2029/0409 (2013.01);
Abstract

A semiconductor device and an erasing method may control a number of times an erase pulse. The erasing method of a flash memory includes the following. Multiple sacrificial memory cells in a block are programmed with different write levels first. When a selected block is erased in response to an erase command, a monitor erase pulse (R) is applied to a well, and then the sacrificial memory cells are verified (S_EV). When the verification fails, a voltage of the monitor erase pulse is increased and then a monitor erase pulse (R) is applied until the verification of the sacrificial memory cells passes. When the verification is passed, a normal erase pulse (Q) is applied to the well based on a voltage of the monitor erase pulse (R) to erase the selected block.


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