Differential programming of two-terminal memory with intrinsic error suppression and wordline coupling

Abstract

Improved differential programming of multiple two-terminal memory cells that define an identifier bit is provided. A differential circuit can be defined by a plurality of resistive memory cells connected to a single bitline of an array, with respective wordlines coupling second terminals of the memory cells to ground (or low voltage). Some disclosed circuits can provide very rapid intrinsic suppression of a non-programmed memory cell(s) defining an identifier bit in response to programming of another memory cell (or group of cells) defining the identifier bit. Differential programming can reduce power consumption and mitigate or avoid invalid data results for an identifier bit.