The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2025

Filed:

Feb. 25, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Tzu-Cheng Lin, Hsinchu, TW;

Chien Rhone Wang, Hsinchu, TW;

Kewei Zuo, Hsinchu, TW;

Ming-Tan Lee, Hsinchu, TW;

Zi-Jheng Liu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 7/00 (2006.01); G06F 30/27 (2020.01); G06F 30/398 (2020.01); G06N 20/00 (2019.01);
U.S. Cl.
CPC ...
G03F 7/706841 (2023.05); G03F 7/70633 (2013.01); G03F 7/706837 (2023.05); G06F 30/27 (2020.01); G06F 30/398 (2020.01); G06N 20/00 (2019.01);
Abstract

The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and machine learning are used to train a classification that correlates the overlay error source factors with overlay metrology categories. The overlay error source factors include tool signals. The trained classification includes a base classification and a Meta classification.


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