The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

Jul. 28, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Giulio Albini, Draper, UT (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
H10N 70/826 (2023.02); H10B 63/80 (2023.02); H10N 70/011 (2023.02); H10N 70/231 (2023.02); H10N 70/882 (2023.02);
Abstract

Methods, systems, and devices for low resistance via contacts in a memory device are described. A via may be formed so as to protrude from a surrounding material. A barrier material may be formed above an array area and also above the via. After a first layer of an access line material is formed above the barrier material, a planarization process may be applied until the top of the via is exposed. The planarization process may remove the access line material and the barrier material from above the via, but the access line material and the barrier material may remain above the array area. The first layer of the access line material may protect the unremoved barrier material during the planarization process. A second layer of the access line material may be formed above the first layer of the access line material and in direct contact with the via.


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