The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

Dec. 27, 2021
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Yi Zheng, Sunnyvale, CA (US);

Er-Xuan Ping, Santa Clara, CA (US);

Assignee:

APPLIED MATERIALS, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 21/04 (2006.01); H01L 29/16 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/401 (2013.01); H01L 21/049 (2013.01); H01L 29/1608 (2013.01); H01L 29/4236 (2013.01);
Abstract

A method of forming a gate structure on a substrate with increased charge mobility. In some embodiments, the method may include depositing an amorphous carbon layer on a silicon carbide layer on the substrate to form a capping layer on the silicon carbide layer, annealing the silicon carbide layer at a temperature of greater than approximately 1800 degrees Celsius, forming a hard mask on the silicon carbide layer by patterning the amorphous carbon layer, etching a trench structure of the gate structure into the silicon carbide layer using the hard mask, removing the hard mask to expose the silicon carbide layer, depositing a silicon dioxide layer on the silicon carbide layer using an ALD process, performing at least one interface treatment on the silicon dioxide layer, depositing a gate oxide layer of the gate structure on the silicon dioxide layer, and depositing a gate material on the gate oxide layer.


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