The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

Feb. 19, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Min-Ying Tsai, Kaohsiung, TW;

Yeur-Luen Tu, Taichung, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/338 (2006.01); H01L 21/02 (2006.01); H01L 21/304 (2006.01); H01L 21/306 (2006.01); H01L 21/336 (2006.01); H01L 21/762 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 27/146 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 21/76251 (2013.01); H01L 21/304 (2013.01); H01L 21/30604 (2013.01); H01L 21/30608 (2013.01); H01L 24/00 (2013.01); H01L 24/80 (2013.01); H01L 25/50 (2013.01); H01L 27/14643 (2013.01); H01L 27/14687 (2013.01); H01L 21/02381 (2013.01); H01L 21/02461 (2013.01); H01L 21/02532 (2013.01); H01L 25/0657 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/94 (2013.01);
Abstract

The present disclosure provides a semiconductor structure, including a first semiconductor device having a first surface and a second surface, the second surface being opposite to the first surface, a semiconductor substrate over the first surface of the first semiconductor device, and a III-V etch stop layer in contact with the second surface of the first semiconductor device. The present disclosure also provides a manufacturing method of a semiconductor structure, including providing a temporary substrate having a first surface, forming a III-V etch stop layer over the first surface, forming a first semiconductor device over the etch stop layer, and removing the temporary substrate by an etching operation and exposing a surface of the III-V etch stop layer.


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