The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2025
Filed:
Jul. 18, 2022
Applicant:
Winbond Electronics Corp., Taichung, TW;
Inventors:
Yao-Ting Tsai, Taichung, TW;
Che-Fu Chuang, Taichung, TW;
Assignee:
Winbond Electronics Corp., Taichung, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/12 (2006.01); G11C 5/06 (2006.01); G11C 29/00 (2006.01); G11C 29/24 (2006.01); G11C 29/52 (2006.01); H10B 41/10 (2023.01); H10B 41/42 (2023.01); G11C 8/14 (2006.01);
U.S. Cl.
CPC ...
G11C 29/72 (2013.01); G11C 5/063 (2013.01); G11C 8/12 (2013.01); G11C 29/24 (2013.01); G11C 29/52 (2013.01); G11C 29/785 (2013.01); H10B 41/10 (2023.02); H10B 41/42 (2023.02); G11C 8/14 (2013.01);
Abstract
A memory array is provided. The memory array includes multiple memory blocks, each including multiple data storage regions and multiple groups of word lines. Each group of word lines extend across one of the memory blocks. The groups of word lines are connected to multiple overlying signal lines through multiple groups of first word line contact regions in the memory blocks and multiple second word line contact regions between the memory blocks.