The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

Jun. 26, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Venkateswara Rao Madduri, Austin, TX (US);

Robert Valentine, Kiryat Tivon, IL;

Mark J. Charney, Lexington, MA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 7/487 (2006.01); G06F 7/499 (2006.01); G06F 7/501 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30036 (2013.01); G06F 7/4876 (2013.01); G06F 7/49947 (2013.01); G06F 7/501 (2013.01); G06F 9/3001 (2013.01); G06F 9/30101 (2013.01); G06F 9/30145 (2013.01);
Abstract

An apparatus and method for multiplying packed real and imaginary components of complex numbers and complex conjugates. For example, one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed real and imaginary data elements; a second source register to store a second plurality of packed real and imaginary data elements; and execution circuitry to execute the decoded instruction. The execution circuitry includes multiplier circuitry to multiply select real and imaginary data elements in the first and second source registers to generate a plurality of real and imaginary products; adder circuitry to add/subtract various real and imaginary products, scale the results according to an immediate of the instruction, round the scaled results; and saturation circuitry to saturate the rounded results.


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