The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2025
Filed:
Dec. 25, 2020
Intel Corporation, Santa Clara, CA (US);
Debendra Das Sharma, Saratoga, CA (US);
Swadesh Choudhary, Mountain View, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Systems, methods, and apparatuses can include transmission-side protocol stack circuitry comprising first cyclic redundancy check (CRC) circuitry to determine first CRC code for a first set of information and to determine second CRC code for a second set of information; and Flit encoding circuitry to encode a first portion of a Flit with the first set of information and the first CRC code, the Flit encoding circuitry to encode a second portion of the Flit with the second set of information and the second CRC code. Receiver-side protocol stack circuitry can include a low-latency path comprising first CRC check circuitry to perform a CRC check on a first portion of a received Flit. Receiver-side protocol stack circuitry can include a non-low-latency path comprising forward error correction (FEC) decoder circuitry to perform FEC on received Flits, and second CRC check circuitry to perform CRC check on received Flits that pass FEC.