The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 2024
Filed:
Jun. 07, 2021
Intel Corporation, Santa Clara, CA (US);
Sandipan Kundu, Hillsboro, OR (US);
Ajay Balankutty, Hillsboro, OR (US);
Bong Chan Kim, Hillsboro, OR (US);
Yutao Liu, Hillsboro, OR (US);
Jihwan Kim, Portland, OR (US);
Kai Yu, Portland, OR (US);
Gurmukh Singh, Gilbert, AZ (US);
Stephen Kim, Beaverton, OR (US);
Richard Packard, Livermore, CO (US);
Frank O'Mahony, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A quadrature clock generator that takes advantage of the inherently low delay of a shunt-series inductively peaked clock buffer to generate quadrature clocks with the high jitter performance using just one additional stage in Q path compared to I path. The generator includes a delay cell that uses shunt-series peaking and uses a resistive DAC in series with the shunt inductor to provide a large delay range with good jitter characteristics. The resistive DAC can be placed near a real or a virtual ground to minimize capacitive loading on the signal path. This delay cell can provide greater than 2× delay tuning range and is suitable for clocks at high frequencies. This delay cell can also be used as a ring oscillator with large frequency tuning range. A low voltage differential signaling termination switch control that uses feed forward mechanism to control termination impedance of device in a receiver.