The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Apr. 19, 2022
Applicant:

Socionext Inc., Kanagawa, JP;

Inventors:

Hirotaka Takeno, Yokohama, JP;

Atsushi Okamoto, Yokohama, JP;

Wenzhen Wang, Yokohama, JP;

Assignee:

SOCIONEXT INC., Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01); H01L 23/495 (2006.01); H01L 23/528 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H03K 19/1735 (2013.01); H01L 23/49562 (2013.01); H01L 29/785 (2013.01);
Abstract

A semiconductor device has: a first chip having a substrate and a first wiring layer; and a second wiring layer formed on a second surface of the substrate. The second wiring layer has a first power supply line, and a second power supply line. The first chip has a first ground line, a third power supply line, a fourth power supply line, vias formed in the substrate and connecting the first power supply line and the third power supply line, a first area in which the first ground line and the fourth power supply line are arranged, and a first circuit connected between the first ground line and the third power supply line. A switch is connected between the first power supply line and the second power supply line. In a plan view, the third power supply line, the vias, and the first circuit are arranged in the first area.


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