The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Feb. 04, 2022
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Cheng-Ta Yang, Kaohsiung, TW;

Lu-Ping Chiang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H10B 41/30 (2023.01); H10B 41/40 (2023.01); H10B 41/42 (2023.01); H10B 41/49 (2023.01);
U.S. Cl.
CPC ...
H01L 29/7883 (2013.01); H01L 29/40114 (2019.08); H01L 29/42324 (2013.01); H01L 29/42364 (2013.01); H01L 29/4916 (2013.01); H01L 29/66825 (2013.01); H10B 41/30 (2023.02); H10B 41/40 (2023.02); H10B 41/42 (2023.02); H10B 41/49 (2023.02);
Abstract

A flash memory device is provided. The flash memory device includes a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, a first polycrystalline silicon layer and a second polycrystalline silicon layer. The first dielectric layer is formed on the substrate located in a first region of a peripheral region, the second dielectric layer is formed on the substrate located in a second region of the peripheral region, and the third dielectric layer is formed on the substrate located in an array region. A bottom surface of the third dielectric layer is lower than a bottom surface of the second dielectric layer. The first polycrystalline silicon layer is formed on the first and the second dielectric layers. The second polycrystalline silicon layer is formed on the third dielectric layer.


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