The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Sep. 28, 2021
Applicant:

Nuvoton Technology Corporation Japan, Kyoto, JP;

Inventors:

Kaname Motoyoshi, Hyogo, JP;

Masatoshi Kamitani, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 23/66 (2006.01); H01L 25/16 (2023.01); H01L 29/20 (2006.01); H03F 1/02 (2006.01); H03F 3/195 (2006.01); H03F 3/213 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7786 (2013.01); H01L 23/66 (2013.01); H01L 25/16 (2013.01); H01L 29/2003 (2013.01); H03F 1/0288 (2013.01); H03F 3/195 (2013.01); H03F 3/213 (2013.01); H01L 2223/665 (2013.01); H01L 2223/6655 (2013.01); H01L 2223/6672 (2013.01); H03F 2200/294 (2013.01); H03F 2200/447 (2013.01); H03F 2200/451 (2013.01);
Abstract

A monolithic semiconductor device includes: a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; a first transistor disposed on the substrate and including the first nitride semiconductor layer and the second nitride semiconductor layer, the first transistor being of a high-electron-mobility transistor (HEMT) type for power amplification; and a first bias circuit disposed on the substrate and including a second transistor of the HEMT type disposed outside a propagation path of a radio-frequency signal inputted to the first transistor, the first bias circuit applying bias voltage to a gate of the first transistor.


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