The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Feb. 17, 2022
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Wei-Lun Huang, Tainan, TW;

Chia-Ling Wang, Yunlin County, TW;

Chia-Wen Lu, Tainan, TW;

Ta-Wei Chiu, Changhua County, TW;

Ping-Hung Chiang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66704 (2013.01); H01L 21/823462 (2013.01); H01L 29/401 (2013.01); H01L 29/42364 (2013.01);
Abstract

A manufacturing method of a semiconductor device includes the following steps. A first recess and a second recess are formed in a first region and a second region of a semiconductor substrate, respectively. A bottom surface of the first recess is lower than a bottom surface of the second recess in a vertical direction. A first gate oxide layer and a second gate oxide layer are formed concurrently. At least a portion of the first gate oxide layer is formed in the first recess, and at least a portion of the second gate oxide layer is formed in the second recess. A removing process is performed for removing a part of the second gate oxide layer. A thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer after the removing process.


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