The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Jun. 03, 2024
Applicant:

Diodes Incorporated, Plano, TX (US);

Inventors:

Chih-Hsiang Hsu, New Taipei, TW;

Tao Long, Shanghai, CN;

Pin-Hao Huang, New Taipei, TW;

Peng Chun Chen, New Taipei, TW;

Assignee:

Diodes Incorporated, Plano, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0336 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/73 (2006.01); H01L 29/739 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0607 (2013.01); H01L 29/66007 (2013.01); H01L 29/7308 (2013.01);
Abstract

The power semiconductor device comprises a base that includes a substrate and an epitaxial layer located above the substrate, with the base comprising a unit area and a peripheral area surrounding the unit area. A junction layer is located within the peripheral area and above the epitaxial layer. A barrier layer is located within the unit area and above the epitaxial layer. A first electrode is located on the junction layer and a second electrode is located on the barrier layer. The epitaxial layer includes a doped channel located within the peripheral area, extending between the junction layer and the base substrate. Current flows from the substrate through the doped channel and the junction layer to the first electrode.


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