The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Feb. 07, 2023
Applicant:

Monolithic 3d Inc., Klamath Falls, OR (US);

Inventors:

Zvi Or-Bach, Haifa, IL;

Jin-Woo Han, San Jose, CA (US);

Brian Cronquist, Klamath Falls, OR (US);

Assignee:

Monolithic 3D Inc., Klamath Falls, OR (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/473 (2006.01); H01L 23/66 (2006.01); H01L 25/16 (2023.01); H10B 80/00 (2023.01);
U.S. Cl.
CPC ...
H01L 24/08 (2013.01); H01L 23/473 (2013.01); H01L 23/66 (2013.01); H01L 24/80 (2013.01); H01L 25/16 (2013.01); H01L 25/167 (2013.01); H10B 80/00 (2023.02); H01L 2223/6616 (2013.01); H01L 2223/6627 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/8013 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1011 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1443 (2013.01);
Abstract

A 3D semiconductor device comprising: a first level; and a second level, wherein said first level comprises single crystal silicon and a plurality of logic circuits, wherein said plurality of logic circuits each comprise first transistors, wherein said second level is disposed above said first level and comprises a plurality of arrays of memory cells, said second level comprises a plurality of second transistors, wherein each of said memory cells comprises at least one of said second transistors, wherein said first level is bonded to said second level, wherein said bonded comprises regions of oxide to oxide bonds, wherein said bonded comprises regions of metal to metal bonds; and a thermal isolation layer disposed between said first level and said second level, wherein said thermal isolation layer provides a greater than 20° C. differential temperature between said first level and said second level during nominal operation of said device.


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