The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 2024
Filed:
Oct. 19, 2023
Adeia Semiconductor Solutions Llc, San Jose, CA (US);
Benjamin D. Briggs, Waterford, NY (US);
Jessica Dechene, Latham, NY (US);
Elbert Huang, Carmel, NY (US);
Joe Lee, Niskayuna, NY (US);
Thedorus E. Standaert, Clifton Park, NY (US);
Adeia Semiconductor Solutions LLC, San Jose, CA (US);
Abstract
A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.