The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Oct. 19, 2022
Applicant:

Enkris Semiconductor, Inc., Suzhou, CN;

Inventors:

Peng Xiang, Suzhou, CN;

Kai Cheng, Suzhou, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C30B 25/04 (2006.01); C30B 25/18 (2006.01); C30B 29/40 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02694 (2013.01); C30B 25/04 (2013.01); C30B 25/183 (2013.01); C30B 25/186 (2013.01); C30B 29/406 (2013.01); H01L 21/02378 (2013.01); H01L 21/02381 (2013.01); H01L 21/02389 (2013.01); H01L 21/0242 (2013.01); H01L 21/02458 (2013.01); H01L 21/0254 (2013.01); H01L 21/02576 (2013.01); H01L 21/0262 (2013.01);
Abstract

Disclosed is a preparation method for a semiconductor structure. The semiconductor structure includes: a substrate; an epitaxial layer and an epitaxial structure that are stacked on the substrate in sequence. The epitaxial layer is doped with a doping element. In the forming process, a sacrificial layer is formed on the epitaxial layer, and the sacrificial layer is repeatedly etched, such that a concentration of the doping element in the epitaxial layer is lower than a preset value. In this application, the sacrificial layer is formed on the epitaxial layer, and the sacrificial layer is repeatedly etched, such that the concentration of the doping element in the epitaxial layer is lower than the preset value, so as to prevent the doping element in the epitaxial layer from being precipitated upward into an upper-layer structure, ensure the mobility of electrons in a channel layer, and improve the performance of a device.


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