The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 2024
Filed:
Feb. 14, 2023
Integrated Silicon Solution Inc., Milpitas, CA (US);
Hyeon Jae Lee, Milpitas, CA (US);
Jeong Ho Bang, Milpitas, CA (US);
Wol Jin Lee, Milpitas, CA (US);
Ki Hyung Ryoo, Milpitas, CA (US);
Kwang Rae Cho, Milpitas, CA (US);
Sun Byeong Yoon, Milpitas, CA (US);
INTEGRATED SILICON SOLUTION INC., Milpitas, CA (US);
Abstract
A memory interface circuitry includes a clock generator to convert the first clock signal into a second clock signal, a state machine to generate a test signal according to the second clock signal, a data pattern generator to generate a plurality of pre-defined data, a read register to sequentially output the plurality of pre-defined data, an I/O interface to capture a plurality of data from the plurality of pre-defined data according to a write strobe signal, a write register to receive and store the plurality of data from the I/O interface, and a comparator to compare the plurality of pre-defined data with the plurality of data to generate a test result. The test result is configured to verify an operation of the I/O interface.