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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12182571 B1

PDFFull Text
Date of Patent:
Dec. 31, 2024

Filed:

Jan. 23, 2023

Systems, methods, and apparatuses for tile load, multiplication and accumulation

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Robert Valentine, Kiryat Tivon, IL;

Menachem Adelman, Haifa, IL;

Milind B. Girkar, Sunnyvale, CA (US);

Zeev Sperber, Zichron Yackov, IL;

Mark J. Charney, Lexington, MA (US);

Bret L. Toll, Hillsboro, OR (US);

Rinat Rappoport, Haifa, IL;

Jesus Corbal, King City, OR (US);

Stanislav Shwartsman, Haifa, IL;

Dan Baum, Haifa, IL;

Igor Yanover, Yokneam Illit, IL;

Alexander F. Heinecke, San Jose, CA (US);

Barukh Ziv, Haifa, IL;

Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);

Yuri Gebil, Nahariya, IL;

Raanan Sade, Kibutz Sarid, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

NICHOLSON DE VOS WEBSTER & ELLIOTT LLP

Primary Examiner:

Steven G Snyder

Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 7/485 (2006.01); G06F 7/487 (2006.01); G06F 7/76 (2006.01); G06F 9/38 (2018.01); G06F 17/16 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30036 (2013.01); G06F 7/485 (2013.01); G06F 7/4876 (2013.01); G06F 7/762 (2013.01); G06F 9/3001 (2013.01); G06F 9/30032 (2013.01); G06F 9/30043 (2013.01); G06F 9/30109 (2013.01); G06F 9/30112 (2013.01); G06F 9/30134 (2013.01); G06F 9/30145 (2013.01); G06F 9/30149 (2013.01); G06F 9/3016 (2013.01); G06F 9/30185 (2013.01); G06F 9/30196 (2013.01); G06F 9/3818 (2013.01); G06F 9/3836 (2013.01); G06F 17/16 (2013.01); G06F 2212/454 (2013.01);
Abstract

Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in the form of decode circuitry to decode an instruction having fields for an opcode, a destination matrix operand identifier, and source memory information, and execution circuitry to execute the decoded instruction to load groups of strided data elements from memory into configured rows of the identified destination matrix operand to memory.

Find Patent Forward Citations

Valentine, Robert. (2024). Systems, methods, and apparatuses for tile load, multiplication and accumulation (U.S. Patent No. 12182571). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12182571

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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