The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Oct. 05, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Andrea Martinelli, Bergamo, IT;

Christophe Vincent Antoine Laurent, Agrate Brianza, IT;

Claudio Nava, Cornate d'Adda, IT;

Marco Defendi, Sulbiate, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); G06F 3/06 (2006.01); G06F 11/10 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0644 (2013.01); G06F 3/0604 (2013.01); G06F 3/0683 (2013.01); G06F 11/1068 (2013.01); G11C 11/221 (2013.01); G11C 11/2253 (2013.01); G11C 11/2273 (2013.01); G11C 11/4087 (2013.01); G11C 11/4091 (2013.01); G11C 29/52 (2013.01);
Abstract

Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or layer). Each of the memory tiles may include a respective circuit level or layer associated with circuitry configured to operate the respective array of memory cells. The memory device may also include circuitry for communicating data between the memory cells of the set of memory tiles and an input/output component. Aspects of the circuitry for communicating the data may be subdivided into repeatable blocks each configured to communicate one or more bits, and the repeatable blocks and other aspects of the circuitry for communicating the data is distributed across the circuit layer of two or more of the set of memory tiles.


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